1. Technical Field
The inventive concept relates to a semiconductor memory device, and more particularly, to a resistive memory device and a fabrication method thereof.
2. Related Art
Resistive memory devices are memory devices using a programmable resistance change material as a data storage node, and a level of data stored in the resistive memory device is divided according to a resistance value of a resistance change material.
Phase-change random access memory devices (PCRAMs) are a typical example of the resistive memory devices. The PCRAMs use a chalcogenide material as a phase-change material, and store data using a difference in a resistance value changed according to phase transition of a phase-change material between an amorphous state and a crystalline state.
Recently, a structure, in which a phase-change material is formed in a confined type and interference between adjacent cells and a reset current are reduced, is suggested, and FIGS. 1A to 1H illustrate a method of fabricating a conventional resistive memory device.
Referring to FIG. 1A, an interlayer insulating layer 103 and a buffer layer 105 are sequentially formed on a semiconductor substrate 101, in which a bottom structure is formed. A first hole 107, exposing a predetermined portion of the semiconductor substrate 101, is formed. A heating electrode 109 is formed in a lower portion of the first hole 107. The interlayer insulating layer 103 may include an oxide, and the buffer layer 105 may include a nitride.
As illustrated in FIG. 1B, a liner insulating layer 111 is formed on the semiconductor substrate including the heating electrode 109. Here, the liner insulating layer 111 may include a material having the same etch characteristic as or similar etch characteristic from the etch characteristic of the buffer layer 105.
As illustrated in FIG. 1C, a first insulating layer 113 is formed on the semiconductor substrate, including the liner insulating layer 111, to fill the inside of the first hole 107. The first insulating layer 113 is planarized and recessed in the first hole 107 to a predetermined height. The first insulating layer 113 may include a material having an etch characteristic that is different than an etch characteristic of the buffer layer 105 and an etch characteristic of the liner insulating layer 111. For example, the first insulating layer 113 may include spin on dielectric (SOD).
As illustrated in FIG. 1D, a spacer insulating layer is formed on the semiconductor substrate, including the first insulating layer 113, and then etched to form a spacer 115 on an inner wall of the first hole 107. The first insulating layer 113 is then removed to form a second hole 117, as illustrated in FIG. 1E.
After the second hole 117 is formed, a second insulating layer 119 is formed on the semiconductor substrate, including the second hole 117. At this time, since the second hole 117 has a structure in which an upper diameter is narrow and a lower diameter is wide, the second insulating layer 119 is buried so that a void is formed in a lower portion of the second hole 117. The second insulating layer 119 may include a material having the same etch characteristic as or a different etch characteristic from the etch characteristic of the buffer layer 105 and the liner insulating layer 111.
Therefore, the second I insulating layer 119 is removed to a predetermined target depth through an etching process to obtain a keyhole structure as illustrated in FIG. 1G.
After the keyhole structure is formed, a phase-change material pattern 121 and an upper electrode 123 are formed in the keyhole structure, as illustrated in FIG. 1H.
The PCRAM having the keyhole structure is suggested to overcome a limit of an exposure and etch process for forming a fine contact having a nano critical dimension, and the PCRAM is advantageous to reduce a reset current through reduction in a contact area between the phase-change material pattern 121 and the heating electrode 109.
However, in the ultra-fine memory device, the size of the unit memory device may reduced as illustrated in FIGS. 1A to 1G, but a space between cells is also reduced. In particular, when a crystalline state of the phase-change material is changed by Joule's heat, heat transferred to the phase-change material pattern 121 from the heating electrode may be transferred to adjacent cells. Thus, a thermal effect between the adjacent cells is increased as the space between the cells is reduced.
Further, to form the keyhole structure using the conventional fabrication method of the PCRAM, the process of forming the spacer, the process of forming the first insulating layer, the process of removing and recessing the first insulating layer, the process of forming the second insulating layer, and the process of removing the second insulating layer are performed. Therefore, the fabrication process is complicated, and thus a processing time is also increased.